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solaris:generic_events.3cpc

generic_events


NAME

generic_events - generic performance counter events

DESCRIPTION

The Oracle Solaris cpc(3CPC) subsystem implements a number of predefined, generic performance counter events. Each generic event maps onto a single platform specific event and one or more optional attributes. Each hardware platform only need support a subset of the total set of generic events.

The defined generic events are:

PAPI_br_cn

Conditional branch instructions

PAPI_br_ins

Branch instructions

PAPI_br_msp

Conditional branch instructions mispredicted

PAPI_br_ntk

Conditional branch instructions not taken

PAPI_br_prc

Conditional branch instructions correctly predicted

PAPI_br_tkn

Conditional branch instructions taken

PAPI_br_ucn

Unconditional branch instructions

PAPI_bru_idl

Cycles branch units are idle

PAPI_btac_m

Branch target address cache misses

PAPI_ca_cln

Requests for exclusive access to clean cache line

PAPI_ca_inv

Requests for cache invalidation

PAPI_ca_itv

Requests for cache line intervention

PAPI_ca_shr

Request for exclusive access to shared cache line

PAPI_ca_snp

Request for cache snoop

PAPI_csr_fal

Failed conditional store instructions

PAPI_csr_suc

Successful conditional store instructions

PAPI_csr_tot

Total conditional store instructions

PAPI_fad_ins

Floating point add instructions

PAPI_fdv_ins

Floating point divide instructions

PAPI_fma_ins

Floating point multiply and add instructions

PAPI_fml_ins

Floating point multiply instructions

PAPI_fnv_ins

Floating point inverse instructions

PAPI_fp_ins

Floating point instructions

PAPI_fp_ops

Floating point operations

PAPI_fp_stal

Cycles the floating point unit stalled

PAPI_fpu_idl

Cycles the floating point units are idle

PAPI_fsq_ins

Floating point sqrt instructions

PAPI_ful_ccy

Cycles with maximum instructions completed

PAPI_ful_icy

Cycles with maximum instruction issue

PAPI_fxu_idl

Cycles when units are idle

PAPI_hw_int

Hardware interrupts

PAPI_int_ins

Integer instructions

PAPI_tot_cyc

Total cycles

PAPI_tot_iis

Instructions issued

PAPI_tot_ins

Instructions completed

PAPI_vec_ins

VectorSIMD instructions

PAPI_l1_dca

Level 1 data cache accesses

PAPI_l1_dch

Level 1 data cache hits

PAPI_l1_dcm

Level 1 data cache misses

PAPI_l1_dcr

Level 1 data cache reads

PAPI_l1_dcw

Level 1 data cache writes

PAPI_l1_ica

Level 1 instruction cache accesses

PAPI_l1_ich

Level 1 instruction cache hits

PAPI_l1_icm

Level 1 instruction cache misses

PAPI_l1_icr

Level 1 instruction cache reads

PAPI_l1_icw

Level 1 instruction cache writes

PAPI_l1_ldm

Level 1 cache load misses

PAPI_l1_stm

Level 1 cache store misses

PAPI_l1_tca

Level 1 cache accesses

PAPI_l1_tch

Level 1 cache hits

PAPI_l1_tcm

Level 1 cache misses

PAPI_l1_tcr

Level 1 cache reads

PAPI_l1_tcw

Level 1 cache writes

PAPI_l2_dca

Level 2 data cache accesses

PAPI_l2_dch

Level 2 data cache hits

PAPI_l2_dcm

Level 2 data cache misses

PAPI_l2_dcr

Level 2 data cache reads

PAPI_l2_dcw

Level 2 data cache writes

PAPI_l2_ica

Level 2 instruction cache accesses

PAPI_l2_ich

Level 2 instruction cache hits

PAPI_l2_icm

Level 2 instruction cache misses

PAPI_l2_icr

Level 2 instruction cache reads

PAPI_l2_icw

Level 2 instruction cache writes

PAPI_l2_ldm

Level 2 cache load misses

PAPI_l2_stm

Level 2 cache store misses

PAPI_l2_tca

Level 2 cache accesses

PAPI_l2_tch

Level 2 cache hits

PAPI_l2_tcm

Level 2 cache misses

PAPI_l2_tcr

Level 2 cache reads

PAPI_l2_tcw

Level 2 cache writes

PAPI_l3_dca

Level 3 data cache accesses

PAPI_l3_dch

Level 3 data cache hits

PAPI_l3_dcm

Level 3 data cache misses

PAPI_l3_dcr

Level 3 data cache reads

PAPI_l3_dcw

Level 3 data cache writes

PAPI_l3_ica

Level 3 instruction cache accesses

PAPI_l3_ich

Level 3 instruction cache hits

PAPI_l3_icm

Level 3 instruction cache misses

PAPI_l3_icr

Level 3 instruction cache reads

PAPI_l3_icw

Level 3 instruction cache writes

PAPI_l3_ldm

Level 3 cache load misses

PAPI_l3_stm

Level 3 cache store misses

PAPI_l3_tca

Level 3 cache accesses

PAPI_l3_tch

Level 3 cache hits

PAPI_l3_tcm

Level 3 cache misses

PAPI_l3_tcr

Level 3 cache reads

PAPI_l3_tcw

Level 3 cache writes

PAPI_ld_ins

Load Instructions

PAPI_lst_ins

Loadstore Instructions

PAPI_lsu_idl

Cycles load store units are idle

PAPI_mem_rcy

Cycles stalled waiting for memory reads

PAPI_mem_scy

Cycles stalled waiting for memory accesses

PAPI_mem_wcy

Cycles stalled waiting for memory writes

PAPI_prf_dm

Data prefetch cache misses

PAPI_res_stl

Cycles stalled on any resource

PAPI_sr_ins

Store Instructions

PAPI_stl_ccy

Cycles with no instructions completed

PAPI_syc_ins

Synchronization instructions completed

PAPI_tlb_dm

Data TLB misses

PAPI_tlb_im

Instruction TLB misses

PAPI_tlb_sd

TLB shootdowns

PAPI_tlb_tl

Total TLB misses

The tables below define mappings of generic events to platform events and any associated attribute for all supported platforms.

Intel Core2 Processors

Fixed-function counters do not require Event Code and Unit Mask. The generic event to fixed-function counter event mappings available are:

Intel Processor 5500 Family (Core i7)

For fixed-function counter mappings refer to the Intel Core2 listing above.

Intel Atom Processors

For fixed-function counter mappings refer to the Intel Core2 listing above.

AMD Opteron Family 0xF Processor

AMD Opteron Family 0x10 Processors

Intel Pentium IV Processor

Intel Pentium Pro/II/III Processor

Niagara T1 Processor

Niagara T2/T2+/T3 Processor

SPARC64 X/X+/XII Processor

SPARC T4 Processor

SPARC M5/T5/M6 Processor

ATTRIBUTES

See attributes(7) for descriptions of the following attributes:

SEE ALSO

cpc(3CPC), attributes(7)

NOTES

Generic names prefixed with “PAPI_” are taken from the University of Tennessee’s PAPI project, http://icl.cs.utk.edu/papi.


solaris/generic_events.3cpc.txt · Last modified: 2023/07/19 08:58 by A User Not Logged in